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LZ23H3V1 description the LZ23H3V1 is a 1/3-type (6.0 mm) solid-state image sensor that consists of pn photo-diodes and ccds (charge-coupled devices). with approximately 1 090 000 pixels (1 217 horizontal x 893 vertical), the sensor provides a stable high- resolution color image. features optical size : number of effective pixels e approx. 1 000 k; 6.6 mm e approx. 790 k; 5.9 mm (compatible with xga format) interline scan format square pixel number of effective pixels : 1 174 (h) x 884 (v) number of optical black pixels e horizontal : 3 front and 40 rear e vertical : 7 front and 2 rear number of dummy bits e horizontal : 22 e vertical : 2 pixel pitch : 4.6 m (h) x 4.6 m (v) r, g, and b primary color mosaic filters supports monitoring mode low fixed-pattern noise and lag no burn-in and no image distortion blooming suppression structure built-in output amplifier built-in overflow drain voltage circuit and reset gate voltage circuit variable electronic shutter package : 16-pin shrink-pitch wdip [ceramic] (wdip016-n-0500c) row space : 12.70 mm pin connections precautions the exit pupil position of lens should be 15 to 50 mm from the top surface of the ccd. refer to "precautions for ccd area sensors" for details. (1 024) 1 000 k pixels 1 156 790 k pixels 866 (768) (5.9 mm) 6.6 mm in the absence of confirmation by device specification sheets, sharp takes no responsibility for any defects that may occur in equipment using any sharp devices shown in catalogs, data books, etc. contact sharp in order to obtain the latest device specification sheets before using any sharp device. 1 LZ23H3V1 1/3-type interline color ccd area sensor with 1 090 k pixels 1od 2gnd 3ofd 4pw 5 rs 6nc 7 h1 8 16 15 14 13 12 11 10 9 h2 os gnd v1a v1b v2 v3a v3b v4 16-pin shrink-pitch wdip top view (wdip016-n-0500c)
LZ23H3V1 2 pin description symbol pin name od output transistor drain os output signals rs reset transistor clock v1a , v1b , v2 , v3a , v3b , v4 vertical shift register clock h1 , h2 horizontal shift register clock pw p-well gnd ground nc no connection overflow drain ofd absolute maximum ratings (t a = +25 ?c) parameter symbol rating unit output transistor drain voltage v od 0 to +18 v reset gate clock voltage v rs internal output v vertical shift register clock voltage v v v pw to +18 v horizontal shift register clock voltage v h e0.3 to +12 v voltage difference between p-well and vertical clock v pw -v v e29 to 0 v storage temperature t stg e40 to +85 ?c ambient operating temperature t opr e20 to +70 ?c 2 note notes : 1. do not connect to dc voltage directly. when ofd is connected to gnd, connect v od to gnd. overflow drain clock is applied below 27 vp-p. 2. do not connect to dc voltage directly. when rs is connected to gnd, connect v od to gnd. reset gate clock is applied below 8 vp-p. 3. when clock width is below 10 s, and clock duty factor is below 0.1%, voltage difference between vertical clocks will be below 28 v. 1 v internal output v ofd overflow drain voltage 3 v 0 to +15 v v -v v voltage difference between vertical clocks
LZ23H3V1 3 recommended operating conditions parameter symbol min. typ. max. unit note ambient operating temperature t opr 25.0 ?c output transistor drain voltage v od 14.55 15.0 15.45 v notes : 1. use the circuit parameter indicated in "system configuration example" , and do not connect to dc voltage directly. 2. v pw is set below v vl that is low level of vertical shift register clock, or is used with the same power supply that is connected to v l of v driver ic. 3. operation frequency is 14.32 mhz. 4. operation frequency is 18.00 mhz. * to apply power, first connect gnd and then turn on v od . after turning on v od , turn on pw first and then turn on other powers and pulses. do not connect the device to or disconnect it from the plug socket while power is being applied. 1 v 26.5 24.5 v ofd overflow drain clock p-well voltage v pw e10.0 v vl v2 ground gnd 0.0 v v e8.5 e9.0 e9.5 v v1al , v v1bl , v v2l v v3al , v v3bl , v v4l vertical shift register clock low level intermediate level high level v v1ai , v v1bi , v v2i v v3ai , v v3bi , v v4i v v1ah , v v1bh v v3ah , v v3bh 14.55 0.0 15.0 15.45 v v low level horizontal shift register clock v h1l , v h2l e0.05 0.0 0.05 v high level v h1h , v h2h 4.5 5.0 5.5 v 1 v 5.5 5.0 4.5 v rs reset gate clock p-p level reset gate clock frequency f rs 14.32 mhz 3 horizontal shift register clock frequency f h1 , f h2 14.32 mhz 3 vertical shift register clock frequency f v1a , f v1b , f v2 f v3a , f v3b , f v4 10.88 khz 3 4 khz 13.47 4 mhz 18.00 4 mhz 18.00 p-p level
LZ23H3V1 4 characteristics (drive method : 1/30 s frame accumulation) (t a = +25 ?c, operating conditions : the typical values specified in " recommended operating conditions ". color temperature of light source : 3 200 k, ir cut-off filter (cm-500, 1 mmt) is used.) parameter symbol min. typ. max. unit note standard output voltage v o 150 mv 2 photo response non-uniformity prnu 10 % 3 saturation output voltage v sat 450 530 mv 4 dark output voltage v dark 0.5 3.0 mv 1, 6 dark signal non-uniformity dsnu 0.5 2.0 mv 1, 7 sensitivity (green channel) r 105 150 mv 8 smear ratio smr e75 e65 db 9 notes : within the recommended operating conditions of v od , v ofd of the internal output satisfies with abl larger than 500 times exposure of the standard exposure conditions, and v sat larger than 330 mv. 1. t a = +60 ?c 2. the average output voltage of g signal under uniform illumination. the standard exposure conditions are defined as when vo is 150 mv. 3. the image area is divided into 10 x 10 segments under the standard exposure conditions. each segment's voltage is the average output voltage of all pixels within the segment. prnu is defined by (vmax e vmin)/vo, where vmax and vmin are the maximum and minimum values of each segment's voltage respectively. 4. the image area is divided into 10 x 10 segments. each segment's voltage is the average output voltage of all pixels within the segment. v sat is the minimum segment's voltage under 10 times exposure of the standard exposure conditions. the operation of ofdc is high. (for still image capturing) 5. the image area is divided into 10 x 10 segments. each segment's voltage is the average output voltage of all pixels within the segment. v sat is the minimum segment's voltage under 10 times exposure of the standard exposure conditions. the operation of ofdc is low. 6. the average output voltage under non-exposure conditions. 7. the image area is divided into 10 x 10 segments under non-exposure conditions. dsnu is defined by (vdmax e vdmin), where vdmax and vdmin are the maximum and minimum values of each segment's voltage respectively. 8. the average output voltage of g signal when a 1 000 lux light source with a 90% reflector is imaged by a lens of f4, f50 mm. 9. the sensor is exposed only in the central area of v/10 square with a lens at f4, where v is the vertical image size. smr is defined by the ratio of the output voltage detected during the vertical blanking period to the maximum output voltage in the v/10 square. 10. the sensor is exposed at the exposure level corresponding to the standard conditions. ai is defined by the ratio of the output voltage measured at the 1st field during the non-exposure period to the standard output voltage. 11. the sensor is exposed only in the central area of v/10 square, where v is the vertical image size. abl is defined by the ratio of the exposure at the standard conditions to the exposure at a point where blooming is observed. 12. the sensor is exposed at the exposure level corresponding to the standard conditions. lcr is defined by (?v g /v o ) x 100, where ?v g is the difference between the average output voltage of g signal at the 1st field, and that of g signal at the 2nd field. 5 mv 410 330 11 500 abl blooming suppression ratio 10 % 1.0 ai image lag output transistor drain current i od 4.0 8.0 ma 12 % 3.0 lcr line crawling
LZ23H3V1 5 pixel structure 1 pin yyyyyyyyy y yyyyyyy y y yyyyyyy y y yyyyyyy y y yyyyyyy y y yyyyyyy y yyyyyyyyy yyyyyyyyy y yyyyyyy y y yyyyyyy y y yyyyyyy y y yyyyyyy y y yyyyyyy y yyyyyyyyy 1 174 (h) x 884 (v) optical black (2 pixels) optical black (7 pixels) optical black (3 pixels) optical black (40 pixels) color filter array gbgbg rgrgr gbgbg rgrgr gbgbg rgrgr bg bgb gr grg bg bgb gr grg bg bgb gr grg bg bgb gr grg bg bgb gr grg bg bgb gr grg gbgbg rgrgr gbgbg rgrgr gbgbg rgrgr (1, 884) (1 174, 884) (1, 1) (1 174, 1) v3b v1a v1b v3a v1a v1a v3a v1b v3b v1b v3a v3b pin arrangement of the vertical readout clock
LZ23H3V1 6 timing chart notes : 1. do not use these signals immediately after field accumulation mode is transferred to frame accumulation mode for still image capturing. 2. do not use these signals immediately after frame accumulation mode is transferred to field accumulation mode for monitoring mode image. * apply at least an ofd shutter pulse to ofd in each field accumulation mode. * do not use the field signals immediately after frame accumulation mode is transferred to field accumulation mode. v3a v2 v1b v1a vd timing chart example os ofdc ofd v4 v3b (at ofd shutter operation) field accumulation mode field accumulation not for use (note 1) not for use (note 1) not for use (note 2) frame accumulation mode (2 . 3 .. 882 . 883) (2 . 3 .. 882 . 883) (2 . 4 .. 882 . 884) (1 . 3 .. 881 . 883) mode (2 . 3 .. 882 . 883) (number of vertical line) pulse diagram in more detail is shown in the figure q to t after next page. field accumulation mode frame accumulation mode at first frame accumulation mode field accumulation mode at first field accumulation mode qqwer e ' tq ofd v3a ofdc os v4 v3b v2 v1b v1a vd hd shutter speed 1/1 000 s q vertical transfer timing for 14.3 mhz operation field accumulation mode 453 1 6 10 874 875 878 879 882 883 ob2 ob1 ob2 ob5 ob6 2 3 6 7 10 11 14 15 18 19 gb rg gb rg gb rg gb rg gb rg gb rg gb rg gb rg
LZ23H3V1 7 ofd v3a ofdc v4 v3b v2 v1b v1a vd hd (2nd field) e , e ' vertical transfer timing for 14.3 mhz operation frame accumulation mode 453 454 459 463 os e ' 872 874 876 878 880 882 ob2 ob4 ob6 1 3 5 7 9 11 13 15 17 19 rg rg rg rg rg rg rg rg rg rg gb gb gb gb gb gb 884 ob2 gb not for use not for use os e ofd v3a ofdc os v4 v3b v2 v1b v1a vd hd shutter speed 1/1 000 s w vertical transfer timing for 14.3 mhz operation frame accumulation mode at first 453 1 6 10 874 875 878 879 882 883 ob2 gb rg gb rg gb rg not for use * do not use the frame signals immediately after field accumulation is transferred to frame accumulation mode. * do not use the frame signals immediately after field accumulation mode is transferred to frame accumulation mode.
LZ23H3V1 8 ofd v3a ofdc v4 v3b v2 v1b v1a vd hd (1st field) r vertical transfer timing for 14.3 mhz operation frame accumulation mode 906 900 1 6 10 os ob1 ob3 ob5 ob7 2 4 6 8 10 12 14 gb gb gb gb gb gb gb not for use charge swept transfer (658 stages) ofd v3a ofdc os v4 v3b v2 v1b v1a vd hd shutter speed 1/1 000 s t vertical transfer timing for 14.3 mhz operation field accumulation mode at first 906 1 6 10 873 875 877 879 881 883 ob1 rg rg rg rg rg rg not for use * do not use the frame signals immediately after field accumulation mode is transferred to frame accumulation mode. * do not use the field signals immediately after frame accumulation mode is transferred to field accumulation mode.
LZ23H3V1 9 v3a v3b v4 v2 v1b v1a hd readout timing for 14.3 mhz operation field accumulation mode 1 1316, 64 96 40 56 104 88 384 436 508 408 132 48 80 392 536 588 660 30.5 s (436 bits) 41.1 s (588 bits) 91.9 s (1 316 bits) (72 bits) (72 bits) 1316, 1 5.03 s 400 560 552 544 5.03 s v3a v3b v4 v2 v1b v1a hd readout timing for 14.3 mhz operation frame accumulation mode at first 64 96 40 56 104 88 384 436 508 408 132 48 80 392 536 588 660 30.5 s (436 bits) 41.1 s (588 bits) 91.9 s (1 316 bits) (72 bits) (72 bits) 1316, 1 5.03 s 5.03 s 400 560 1316, 1 552 544
LZ23H3V1 10 os rs h2 h1 hd ob (40) ofd v4 v2 horizontal transfer timing for 14.3 mhz operation 1316, 1 132 48 80 64 96 40 56 104 72 92 117.5 40 88 .. 1174 v1a v1b v3a v3b pre scan (22) ob (3) output (1 174) 1 111 v4 v3a v3b v2 v1b v1a hd v4 v2 v1b v1a v3b v3a hd readout timing for 14.3 mhz operation frame accumulation mode 64 40 56 476 548 132 48 (72 bits) 33.2 s (476 bits) 80 96 88 104 1 1316, 1 56 40 104 88 132 48 80 64 96 80 96 88 104 48 64 40 56 1 5.03 s (72 bits) 33.2 s (476 bits) 5.03 s 1316, 1 (1st field) (2nd field) 476 548
LZ23H3V1 11 v1a v1b v4 v3a v3b v2 hd charge swept transfer timing for 14.3 mhz operation 900h 901h 902h 905h 906h 1 132 1316 1306 2 14263850 1306 2 14263850 1312 8 203244 1312 8 203244 1234 658 657 656 1h 2h 3h 4h 5h 6h v4 ofdc os v3b v3a v2 v1b v1a vd hd shutter speed 1/1 000 s q vertical transfer timing for 18.0 mhz operation field accumulation mode ofd 442 449 1 6 10 858 859 862 863 866 867 870 871 874 875 878 879 882 883 ob2 2 ob6 ob5 ob2 ob1 3 6 7 10 11 gb rg gb rg gb rg gb rg gb rg gb rg gb rg gb rg gb rg gb rg * do not use the field signals immediately after frame accumulation mode is transferred to field accumulation mode.
LZ23H3V1 12 v4 ofdc os v3b v3a v2 v1b v1a vd hd shutter speed 1/1 000 s w vertical transfer timing for 18.0 mhz operation frame accumulation mode at first ofd 442 449 1 6 10 858 859 862 863 866 867 870 871 874 875 878 879 882 883 ob2 gb rg gb rg gb rg gb rg gb rg gb rg gb rg not for use * do not use the field signals immediately after frame accumulation mode is transferred to field accumulation mode. * do not use the field signals immediately after frame accumulation mode is transferred to field accumulation mode. v4 ofdc os e v3b v3a v2 v1b v1a vd hd e , e ' vertical transfer timing for 18.0 mhz operation frame accumulation mode ofd 449 450 455 459 856 858 860 862 864 866 868 870 872 874 876 878 880 882 884 ob2 1 ob6 ob4 ob2 357911 gb gb gb gb gb gb gb gb gb gb gb gb gb gb gb rg rg rg rg rg rg (2nd field) not for use not for use os e '
LZ23H3V1 13 v4 ofdc os v3b v3a v2 v1b v1a vd hd r vertical transfer timing for 18.0 mhz operation frame accumulation mode ofd 888 898 1 6 10 ob7 ob5 ob3 ob1 2 4 6 8 gb gb gb gb (1st field) not for use charge swept transfer (668 stages) v4 ofdc os v3b v3a v2 v1b v1a vd hd shutter speed 1/1 000 s t vertical transfer timing for 18.0 mhz operation field accumulation mode at first ofd 898 1 6 10 857 859 861 863 865 867 869 871 873 875 877 879 881 883 ob1 rg rg rg rg rg rg rg rg rg rg rg rg rg rg not for use * do not use the frame signals immediately after field accumulation mode is transferred to frame accumulation mode. * do not use the field signals immediately after frame accumulation mode is transferred to field accumulation mode.
LZ23H3V1 14 v3a v3b v4 v2 v1b v1a hd readout timing for 18.0 mhz operation field accumulation mode 1336, 1 50 70 40 100 110 480 660 725 815 680 500 670 470 535 625 1336, 1 90 132 60 490 690 120 29.7 s (535 bits) 5.00 s (90 bits) 5.00 s (90 bits) 41.1 s (588 bits) 74.2 s (1336 bits) v3a v3b v4 v2 v1b v1a hd readout timing for 18.0 mhz operation frame accumulation mode at first 50 70 40 100 110 480 660 725 815 680 500 670 470 535 625 1336, 1 90 132 60 490 690 120 1336, 1 29.7 s (535 bits) 5.00 s (90 bits) 5.00 s (90 bits) 41.1 s (588 bits) 74.2 s (1 336 bits)
LZ23H3V1 15 v4 v2 hd (1st field) (2nd field) readout timing for 18.0 mhz operation frame accumulation mode v4 v2 hd 1 50 70 40 60 90 110 100 120 132 1 90 585 675 110 70 40 100 100 40 120 60 120 60 110 70 90 50 50 132 1336, 1 32.5 s (585 bits) 585 675 (90 bits) 32.5 s (585 bits) (90 bits) 1336, 1 v1a v1b v3a v3b 5.00 s 5.00 s v1a v1b v3a v3b os rs h2 h1 hd ob (40) ob (3) pre scan (22) ofd v4 v2 horizontal transfer timing for 18.0 mhz operation 132 50 90 70 40 60 120 80 105 137.5 40 .. 1174 110 1336, 1 100 v1a v1b v3a v3b output (1 174) 1 1111111
LZ23H3V1 16 v1a v1b v4 v3a v3b v2 hd charge swept transfer timing for 18.0 mhz operation 888h 889h 890h 897h 898h 1h 2h 3h 4h 5h 6h 1 132 1336 1322 2 18345066 1322 2 18345066 1330 10 26 42 58 1330 10 26 42 58 1234 668 667 666
LZ23H3V1 17 system configuration example + od pw ofd v3b v3a v4 gnd nc h1 h2 os gnd v1a v1b v2 rs v 3b v 3a v 1b v 1a v ma v h v 4 v 2 v l v mb pofd nc v h h2 vh 1bx v 3x v 2x vh 3bx v 4x v ofdh v 1x vh 3ax vh 1ax +3.3 v ofdx h1 rs v l (v pw ) ccd out v ofdh vh 3bx ofdx v 2x v 1x v 3x v dd gnd v 4x vh 3ax vh 1bx vh 1ax + + 1 2 3 4 5 6 7 8 12 24 23 22 21 20 19 18 17 13 11 14 10 15 9 16 2 3 4 5 6 7 8 15 14 1 16 13 12 11 10 9 lr36685 LZ23H3V1 (*1) (*1) v od ofdc 270 pf 100 $ 1 m$ 1 m$ 5.6 k$ 18 k$ 0. 47 f 0. 01 f + + (*1) rs , ofd : use the circuit parameter indicated in this circuit example, and do not connect to dc voltage directly.
packages for ccd and cmos devices 18 package (unit : mm) 0.04 1.66 0.10 package (cerdip) glass lid ccd cross section a-a' 1 8 14.00 0.15 16 9 11.20 0.10 () 12.40 0.15 6.20 0.15 0.60 0.60 7.00 0.15 1.40 0.60 ccd ( : lid's size) 11.20 0.10 () center of effective imaging area and center of package 0.25 0.10 12.70 0.25 0.80 0.05 () 1.05 min. 0.46 typ. 0.90 typ. 2.63 typ. 5.24 max. 3.42 0.25 1.27 0.25 3.90 0.30 2.60 0.20 p-1.78 typ. a' a rotation error of die : a = 1.5? max. m 0.25 16 wdip (wdip016-n-0500c)
precautions for ccd area sensors 1. package breakage in order to prevent the package from being broken, observe the following instructions : 1) the ccd is a precise optical component and the package material is ceramic or plastic. therefore, ? take care not to drop the device when mounting, handling, or transporting. ? avoid giving a shock to the package. especially when leads are fixed to the socket or the circuit board, small shock could break the package more easily than when the package isn?t fixed. 2) when applying force for mounting the device or any other purposes, fix the leads between a joint and a stand-off, so that no stress will be given to the jointed part of the lead. in addition, when applying force, do it at a point below the stand-off part. (in the case of ceramic packages) the leads of the package are fixed with low melting point glass, so stress added to a lead could cause a crack in the low melting point glass in the jointed part of the lead. (in the case of plastic packages) e the leads of the package are fixed with package body (plastic), so stress added to a lead could cause a crack in the package body (plastic) in the jointed part of the lead. 3) when mounting the package on the housing, be sure that the package is not bent. e if a bent package is forced into place between a hard plate or the like, the pack- age may be broken. 4) if any damage or breakage occurs on the sur- face of the glass cap, its characteristics could deteriorate. therefore, ? do not hit the glass cap. ? do not give a shock large enough to cause distortion. ? do not scrub or scratch the glass surface. even a soft cloth or applicator, if dry, could cause dust to scratch the glass. 2. electrostatic damage as compared with general mos-lsi, ccd has lower esd. therefore, take the following anti-static measures when handling the ccd : 1) always discharge static electricity by grounding the human body and the instrument to be used. to ground the human body, provide resistance of about 1 m$ between the human body and the ground to be on the safe side. 2) when directly handling the device with the fingers, hold the part without leads and do not touch any lead. glass cap package lead fixed stand-off fixed lead stand-off low melting point glass 19 precautions for ccd area sensors
3) to avoid generating static electricity, a. do not scrub the glass surface with cloth or plastic. b. do not attach any tape or labels. c. do not clean the glass surface with dust- cleaning tape. 4) when storing or transporting the device, put it in a container of conductive material. 3. dust and contamination dust or contamination on the glass surface could deteriorate the output characteristics or cause a scar. in order to minimize dust or contamination on the glass surface, take the following precautions : 1) handle the ccd in a clean environment such as a cleaned booth. (the cleanliness level should be, if possible, class 1 000 at least.) 2) do not touch the glass surface with the fingers. if dust or contamination gets on the glass surface, the following cleaning method is recommended : ? dust from static electricity should be blown off with an ionized air blower. for anti- electrostatic measures, however, ground all the leads on the device before blowing off the dust. ? the contamination on the glass surface should be wiped off with a clean applicator soaked in isopropyl alcohol. wipe slowly and gently in one direction only. frequently replace the applicator and do not use the same applicator to clean more than one device. note : in most cases, dust and contamination are unavoidable, even before the device is first used. it is, therefore, recommended that the above procedures should be taken to wipe out dust and contamination before using the device. 4. other 1) soldering should be manually performed within 5 seconds at 350 ?c maximum at soldering iron. 2) avoid using or storing the ccd at high tem- perature or high humidity as it is a precise optical component. do not give a mechanical shock to the ccd. 3) do not expose the device to strong light. for the color device, long exposure to strong light will fade the color of the color filters. 20 precautions for ccd area sensors

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